a) Field of the Invention
This invention relates to a method of fabricating a wiring, and more particularly to a method of fabricating a wiring on a planarized insulating film adapted for fabricating a wiring in a large scale integrated circuit (LSI).
b) Description of Related Art
Conventionally, those methods as shown in FIGS. 11 and 12 are known as the method of fabricating a wiring on a planarized insulating film in LSI (for example, refer to JP-A 6-140387).
Referring to FIG. 11, a plurality of MOS transistors are formed on the surface of a semiconductor substrate 1, by the well-known method. In the figure, reference numerals 2a and 2b indicate gate insulating films of the first and second MOS transistors, and reference numerals 3a and 3b indicate gate electrode layers of the first and second MOS transistors. The source and drain regions of the first and second MOS transistors are not shown for the brevity of the figure. A silicon oxide film 4 is formed on the surface of the substrate, covering the step-forming structure including the gate electrode layers 3a and 3b, etc., by chemical vapor deposition (CVD). After deposition of the film 4, the substrate is subjected to annealing in N.sub.2 atmosphere at 850.degree. C. for 30 minutes, to densify the film 4. The film 4 is conformal to the step-forming structure of the underlying surface, and has an uneven surface.
On the surface of silicon oxide film 4, silanol-containing spin-on-glass (SOG) solution is coated by spin coating to have a flat surface. The coated film is subjected first to a low temperature annealing in air at 150.degree. C. for 1 minute to vaporize the solvent, and then to another low temperature annealing in air at 400.degree. C. for 1 minute. The coated film is not perfectly converted to silicon oxide in this state. Then, the coated film is subjected to a high temperature annealing in N.sub.2 atmosphere at 800.degree. C. for 30 minutes. The coated film is then perfectly converted to silicon oxide by this high temperature annealing, to provide a glass film 5 formed of silicon oxide.
If the coated film is directly subjected to the high temperature annealing without subjecting to the low temperature annealing, the glass film 5 may peel off from the silicon film 4 by the rapid contraction of the SOG. For preventing such peeling, the low temperature annealing is performed before the high temperature annealing.
The high temperature annealing is performed to perfectly convert the coated film to silicon oxide. As a result of the high temperature annealing, the etch rate of the glass film 5 in wet etching becomes almost equal to that of the silicon oxide film 4.
A connection hole reaching the gate electrode layer 3a is formed through the silicon oxide film 4. Then, the substrate is subjected to light wet etching by diluted fluoric acid, for removing the native oxide film on the electrode layer 3a in the connection hole. Here, if the glass film 5 has not been subjected to the high temperature annealing, it has a larger etch rate relative to that of the silicon oxide film 4, and may be completely removed by the light wet etching. Therefore, the glass film 5 is subjected to the high temperature annealing to bring the etch rate thereof to be approximately equal to that of the silicon oxide film 4. In this case, when the connection hole is formed and light wet etching by diluted fluoric acid is performed, the flatness of the interlevel insulating film formed of lamination of the films 4 and 5 can be maintained. After the wet etching, a desired wiring layer is formed on the interlevel insulating film.
According to the above-mentioned method of planarizing the insulating film, cracks may be generated in the glass film 5 upon the high temperature annealing. Then, the breakdown voltage of the interlevel insulating film may be degraded.
For avoiding such inconvenience, another planarizing method is proposed, in which the glass film 5 is subjected to only a low temperature annealing below 700.degree. C., without performing any high temperature annealing at a temperature above 700.degree. C., to planarize the film. In this method, the glass film 5 is subjected to a low temperature annealing in the state of FIG. 11. Then, as shown in FIG. 12, the lamination of the films 4 and 5 is etched back by dry etching under the conditions in which the etch rates of the silicon oxide film 4 and the glass film 5 are approximately equal, to planarize the surface of the silicon oxide film 4. After the planarization, the desired connection hole is formed through the insulating film 4, and light wet etching by diluted fluoric acid is performed to remove the native oxide film. Then, a desired wiring layer is formed on the insulating film 4.
According to the above-mentioned planarizing method in which the glass film 5 is not subjected to the high temperature annealing, the range of dry etching conditions which can bring the etching rates of the silicon oxide film 4 and the glass film 5 approximately equal is extremely narrow. Therefore, it was difficult to obtain good uniformity and reproducibility in the etch back treatment. As a countermeasure for this problem, the silicon oxide film 4 may be formed thick and the amount of etch-back may be increased. However, according to this method, the time length for the treatment becomes long and the throughput is lowered.